50-Ohm PCB Trace Design Guide

The 50 Ω standard traces back to coaxial cable design: for a given cable diameter and dielectric, roughly 30 Ω minimizes attenuation and roughly 77 Ω maximizes power handling in air-dielectric coax, and 50 Ω was chosen decades ago as a practical middle ground that balances both reasonably well for general-purpose RF use. Once test equipment, connectors, and RF components standardized on 50 Ω, PCB traces needed to match it to avoid reflections at every transition.

75 Ω remains standard in video and some broadcast RF applications where minimizing loss over long cable runs matters more than power handling, but for the antennas, amplifiers, and general RF modules most PCB designs deal with, 50 Ω is the default and should be assumed unless a specific interface calls for otherwise.

For a microstrip trace (on an outer layer, referenced to one plane below it), impedance depends on trace width, copper weight (which sets trace thickness), the height of dielectric between the trace and the reference plane, and the dielectric constant of that material. Increasing width lowers impedance; increasing dielectric height or lowering Dk raises it. These interact, which is why a 50 Ω trace width on a 0.2 mm dielectric is meaningfully different from a 50 Ω trace width on a 0.5 mm dielectric even with the same copper weight.

This is also why a trace width that was correct on one stackup does not transfer to another: moving to a thinner core, a different copper weight, or a different laminate changes the width needed to hit the same 50 Ω target. Treat trace width as an output of the stackup, not an input you bring from a previous project.

Stripline sits on an internal layer between two reference planes, so the electric field is confined on both sides rather than spreading into air above an outer-layer trace. That tighter confinement means a stripline trace needs to be narrower than a microstrip trace on the same dielectric to reach the same 50 Ω target, because the effective capacitance per unit length is higher with two nearby planes instead of one.

This matters when converting a design between an outer-layer and an internal-layer routing decision: do not reuse a microstrip trace width on a stripline layer and expect the same impedance. If the structure type is not explicit in your routing notes, state it plainly in the RFQ (see how to specify a controlled impedance PCB for the full table format).

Solder mask over an outer-layer microstrip trace adds a thin layer of dielectric above the copper, which slightly increases effective capacitance and typically lowers the measured impedance by a few percent compared to a bare-copper model. State whether your target impedance already accounts for mask, so the fabricator is not compensating for an effect you already modeled (which would overcorrect).

Copper roughness at the dielectric interface has a measurable effect at higher frequencies, mainly on insertion loss rather than characteristic impedance, but it is worth flagging alongside trace geometry for any design pushing into the higher microwave bands—see the high-frequency FAQ on copper roughness for when it becomes significant. Finally, reference-plane continuity matters as much as trace width: a split or gap in the ground plane under a 50 Ω trace creates a local impedance discontinuity no amount of width tuning can fix.