PCB Impedance Tolerance: ±5% vs. ±10%

At ±10%, a documented stackup and a coupon on the production panel is usually sufficient—etch compensation during CAM absorbs normal process variation and the resulting measured impedance lands comfortably inside the window. This is the default tolerance for most digital prototypes and a large share of production boards.

At ±7%, the stackup needs a qualified dielectric set with tighter thickness control, and the coupon strategy usually moves from spot-checking to measuring every panel or every lot, with a documented TDR trace rather than a pass/fail stamp. This tier suits channels with real but not extreme margin requirements: USB 3.x, PCIe Gen 3/4, and DDR-class memory interfaces are common examples.

At ±5%, etch control tightens further, the material set is usually locked to a specific supplier and lot family rather than “FR-4, any qualified source,” and TDR measurement against the agreed structure becomes a stated deliverable rather than a spot check. This tier is appropriate for RF-adjacent digital sections and multi-gigabit differential pairs where the insertion-loss and return-loss budget leaves little room for geometry drift to eat margin.

Start from the channel, not the trace. If a signal integrity simulation or vendor reference design specifies a tolerance, use it—those numbers usually come from an eye-diagram or return-loss budget, not a guess. If no simulation exists, a reasonable default is ±10% for general digital I/O, ±7% for high-speed serial buses operating below roughly 5–6 Gbps, and ±5% for multi-gigabit SerDes, RF-adjacent traces, or any channel where the design margin was already tight before impedance variation entered the picture.

Resist the instinct to specify ±5% across an entire board because one differential pair needs it. Mixed-tolerance boards are normal: control signals and low-speed buses can stay at ±10% while the one or two critical SerDes groups get ±5%, and the fabricator prices the panel based on which groups actually need the tighter process—not a blanket assumption.

Tightening tolerance does not require a different laminate in most cases—it requires tighter control of the processes that already exist: etch factor consistency across the panel, dielectric thickness repeatability within a lot, and more frequent or more detailed coupon measurement. Each of those is a real cost driver because it reduces the yield window a fabricator can accept before scrapping or reworking a panel, and because TDR measurement and reporting take engineering time that a pass/fail visual check does not.

This is also why “just make everything ±5% to be safe” is a false economy: it raises the cost of every panel and every lot for margin the design does not need, without improving reliability on the channels that were already comfortable at ±10%.