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Controlled Impedance PCB Manufacturing

Impedance is a stackup outcome—not a trace-width guess. MOZPCB builds multilayer prototypes and production boards to documented targets, with coupon plans and tolerances your SI team can measure against.

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Multilayer PCB suited for controlled impedance routing
Stackup-controlled multilayer build

Service overview

Controlled impedance PCBs require agreement on dielectric thickness, copper weight, reference planes, trace geometry, and acceptable tolerance before CAM—not after first article. A layout with correct-looking widths but wrong dielectric assumptions will fail tuning even when the board matches the Gerber.

MOZPCB reviews impedance tables alongside fabrication data: which layers reference which planes, whether coplanar or microstrip structures apply, and whether differential pairs need gap control as well as width. We panelize test coupons when the RFQ requires evidence, and we document the stackup the quote assumes against the PCB capabilities process window.

Prototype impedance builds are a core use case. EVT and DVT lots still need a real stackup table, coupon strategy, and a stated tolerance—otherwise first article cannot tell you whether the model or the fab is wrong. We carry the same traveler from prototype into small-batch multilayer production so you are not re-quoting geometry after the design freezes.

Programs range from single 50 Ω lines on a 4-layer board through multi-gigabit differential pairs on 10+ layer stackups and RF-adjacent digital sections on hybrid laminates. Tighter tolerances are available when the geometry and material set support them—stated explicitly in the quote rather than implied.

Prototype controlled impedance builds and test coupons

EVT and DVT lots need the same stackup table, tolerance targets, and coupon plan as production—not a prototype exemption. MOZPCB panels impedance coupons when the RFQ specifies groups and allowed deviation, and can supply TDR reports on agreed structures.

Start from the stackup planning guide and impedance tolerance notes before you freeze trace widths; fabrication releases on multilayer PCB manufacturing reuse the locked stackup after the prototype proves out.

What we offer

  • Stackup design assistance aligned to your impedance targets
  • Single-ended and differential pair control with documented tolerances
  • Microstrip, stripline, and coplanar waveguide geometries
  • Test coupon design and panelization for measurement
  • TDR reports on agreed builds when required
  • Hybrid stackups combining FR-4 and controlled-Dk laminates
  • DFM feedback on reference plane continuity and return-path breaks
  • Coordination with assembly finish and reflow plans that affect impedance
  • Prototype-to-production reuse of the locked stackup and coupon notes

Technical capabilities

  • Typical tolerance ±10% standard; ±7% and ±5% reviewed per construction
  • Dielectric thickness control through agreed laminate sets
  • Line width and space limits tied to copper weight and imaging capability
  • Coupons on production panels or dedicated test panels per agreement
  • Back-drilling for stub reduction on thick high-speed builds
  • 4–32 layer multilayer constructions when the impedance table requires extra planes
Controlled impedance PCB capabilities — confirmed against the approved production stackup, not the nominal trace width alone; final tolerance depends on trace geometry, copper thickness, dielectric construction, surface finish, and test-coupon strategy
Capability Standard support Advanced / conditional support
Impedance types Single-ended and differential impedance Multiple impedance groups on the same board
Common targets 50 Ω and 75 Ω single-ended; 90 Ω and 100 Ω differential Other target values per the customer’s impedance table
Trace structures Surface microstrip and internal stripline Embedded microstrip, coplanar waveguide, and grounded coplanar waveguide
Standard tolerance ±10% ±7% on qualified constructions; ±5% after engineering review
Layer construction Two-layer and multilayer controlled-impedance PCB High-layer-count, HDI, and hybrid-material stackups
Material systems Controlled FR-4 laminate sets Rogers, PTFE, low-loss, and hybrid laminate constructions
Stackup support Customer-provided stackup review Stackup proposal based on target impedance and available materials
Test coupons Production-panel coupon when specified Dedicated coupon structures or multiple impedance groups
Test method TDR measurement against agreed targets Customer-defined sampling and reporting requirements
Via-stub control Standard through-via structures Back-drilling and other stub-reduction methods
Documentation Approved production stackup Final stackup, coupon data, and TDR report when specified
Example stackup notes we expect in a controlled-impedance RFQ (4-layer illustration)
Layer Copper Reference Typical structure
L1 signal 1 oz L2 plane 50 Ω microstrip; mask-included callout
L2 GND 1 oz — Solid reference; avoid splits under controlled nets
L3 PWR / GND 1 oz — Plane or mixed; note any return-path gaps
L4 signal 1 oz L3 plane 50 Ω microstrip or 100 Ω differential
Impedance tolerance vs process cost (confirm on the quote, not assumed)
Tolerance Typical stackup What it requires Best for
±10% Standard FR-4 multilayer Documented stackup + coupon on panel Most digital prototypes
±7% Controlled dielectric / tighter etch Coupon measurement, material lock USB / PCIe / DDR-class channels
±5% Tight geometry + extra coupons TDR on agreed structures, often hybrid/RF laminate RF-adjacent and multi-gigabit pairs
Example impedance requirement table — if trace width and pair spacing are not electrically fixed, mark them “fabricator adjusted” so we can compensate geometry against the approved stackup while holding the target impedance
ID Type Target Tolerance Signal layer Reference layer Structure
Z1 Single-ended 50 Ω ±10% L1 L2 GND Microstrip
Z2 Differential 90 Ω ±10% L3 L2/L4 GND Stripline
Z3 Differential 100 Ω ±7% L6 L5 GND Stripline

Common applications

  • High-speed digital backplanes and switch fabrics
  • DDR and SerDes channels on dense mainboards
  • Ethernet, USB 3.x, and PCIe routing
  • RF-adjacent digital sections requiring stable Dk
  • Industrial vision and acquisition with long matched pairs
  • Multilayer prototypes validating SI before production lock

How the process works

  1. 01

    Requirements intake

    Share Gerber, BOM, drawings, quantities, and any reliability or compliance notes.

  2. 02

    Technical alignment

    We confirm materials, finishes, assembly flow, and test expectations with you.

  3. 03

    Production & inspection

    Manufacturing and assembly follow the agreed traveler with documented checks.

  4. 04

    Delivery

    Packing, labeling, and shipment according to your logistics instructions.

Fabrication & impedance coupons

  • PCB copper plating line
    Plating line
  • Panelized PCBs after fabrication
    Panelized boards
  • Laminate and core material storage
    Laminate store

Related services

Multilayer PCB Manufacturing Services High-Frequency PCB Manufacturer View PCB capabilities Request a quote

Related guides

PCB capabilities table PCB stackup planning for controlled impedance Multilayer PCB manufacturing How to specify a controlled impedance PCB PCB impedance tolerance: ±5% vs ±10% PCB impedance test coupons and TDR testing

Controlled impedance PCB RFQ checklist

This is the information our stackup review needs before CAM—pair it with the Gerber and fabrication-data checklist for the rest of the package.

  • Gerber or ODB++ files
  • Layer stackup (proposed or requested)
  • Target impedance for each group
  • Single-ended or differential type per group
  • Signal layer and reference plane(s) for each group
  • Allowed tolerance (±10% / ±7% / ±5%)
  • Fixed trace width/spacing, or “fabricator adjusted”
  • Coplanar ground spacing, if coplanar structures are used
  • Copper weight and final surface finish
  • Coupon and TDR requirements
  • Report format and sampling/acceptance criteria

FAQ

What should an impedance table include?
Target ohms, tolerance, layer, reference plane(s), trace geometry if fixed, and whether the structure is single-ended or differential. Note coplanar ground spacing if used, and whether solder mask is included in the calculation.
How tight can impedance tolerance be?
±10% is common on standard FR-4 multilayer. ±7% is achievable on many controlled builds; ±5% requires tighter etch control and more coupon testing—priced accordingly.
Do you provide TDR reports?
Yes, when agreed in the RFQ. Specify which nets or coupon structures need reporting and the acceptance format your team expects.
Does surface finish affect impedance?
Slightly, especially on outer-layer microstrip at high frequency. Finish choice should be part of the RFQ when margins are tight—we factor it into review.
Can you build controlled impedance on a prototype lot?
Yes. Prototype quantity does not waive the stackup table. We panelize coupons with the EVT/DVT lot so you can measure before freezing production.
How does multilayer PCB impedance control differ from a 2-layer board?
Inner stripline pairs need assigned reference planes, dielectric thickness, and copper weight—not just outer-layer width. Share the layer map with the impedance table so we quote the construction you will actually release.

Get started

Ready for the next step?

Send your project files and requirements. We will review stackup, assembly, and test needs, then respond with a clear quotation path.

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