How to Specify a Controlled Impedance PCB

Every row in an impedance table should answer the same six questions: what is this group called (ID), is it single-ended or differential (type), what ohm value is the target, what tolerance applies, which layer carries the signal, and which layer or layers serve as the return reference. Leave any of these implicit and the fabricator has to ask, which is exactly the back-and-forth a clean RFQ avoids.

A seventh field—trace structure (microstrip, stripline, or coplanar waveguide)—matters once the board has internal layers, because the same copper weight and dielectric thickness produce different impedance depending on whether the reference plane sits directly below the trace (microstrip) or on both sides of an internal layer (stripline). State the structure explicitly rather than letting the fabricator infer it from the stackup.

Single-ended impedance (commonly 50 Ω or 75 Ω) depends on trace width, copper weight, dielectric thickness to the reference plane, and dielectric constant. One geometry variable—width—is usually the lever a fabricator adjusts to hit the target on a given stackup.

Differential impedance (commonly 90 Ω or 100 Ω) depends on the same variables plus the gap between the two traces in the pair, because the fields from each trace couple and lower the effective impedance as the pair moves closer together. A differential callout without a gap value is underspecified; the fabricator cannot solve for one unknown with two missing variables (width and gap) and no stated coupling.

If your layout tool exports a target impedance but not the width/gap values it modeled, say so in the RFQ rather than back-calculating informally. A wrong assumption here is invisible until TDR measurement disagrees with simulation.

If your trace width and pair spacing are electrically fixed by other constraints (connector pitch, via keep-outs, an existing footprint), state that explicitly and expect the fabricator to compensate through etch factor and, where possible, dielectric selection instead. If they are not fixed, mark them “fabricator adjusted”—this is usually the faster and cheaper path, because it lets the fabricator solve the geometry against the actual lot-measured dielectric rather than your nominal datasheet assumption.

A worked example for a 4-layer board: Z1 is a single-ended 50 Ω microstrip on L1 referenced to L2 ground; Z2 is a 90 Ω differential stripline pair on L3 referenced to L2/L4 ground; Z3 is a tighter-tolerance 100 Ω differential pair on L6 of a higher-layer-count board. All three can mark width and gap as fabricator adjusted and still hit target, because the constraint that matters is the impedance—not the exact mil value a simulator produced on a dielectric thickness the fabricator may build slightly differently.

The most common gap is an impedance table with no reference layer—one engineer assumes the nearest plane, the fabricator assumes another, and the resulting dielectric thickness does not match either assumption. The second most common gap is a differential pair specified with target and tolerance only, no gap, which forces a guess at coupling. The third is leaving coplanar ground spacing off a coplanar-waveguide structure, which is a real third geometry variable, not a cosmetic detail.

A smaller but real issue: not stating whether solder mask is included in the impedance model. Mask adds a small amount of capacitance on outer layers, and ignoring it is a frequent few-percent discrepancy between simulated and measured impedance on microstrip. State it either way so it does not become an unexplained TDR deviation later. Pair your impedance table with the general Gerber and fabrication-data checklist so stackup, finish, and impedance notes travel together in one RFQ package.