HDI PCB Design Guide: Microvias, Stackups, and Cost Drivers

A microvia is a laser-drilled hole, typically 0.1 mm (4 mil) in diameter, connecting one copper layer to the next. Because the laser ablates one dielectric layer at a time, a single microvia spans exactly one layer pair. Reliability hinges on aspect ratio—the ratio of dielectric thickness to hole diameter—which should stay at or below 0.75:1 for dependable plating. A 0.1 mm microvia through 0.075 mm of dielectric is comfortable; the same hole through 0.1 mm of dielectric is not.

When a connection must travel more than one layer, designers choose between stacked microvias (drilled and plated one on top of another, each filled with copper) and staggered microvias (offset laterally, connected by short traces). Stacked vias save space but each level adds a fill-and-planarize cycle, and thermal cycling stress concentrates at the stacked interfaces. Staggered vias are cheaper and historically more reliable—use them wherever your density budget allows.

HDI stackups are described by how many microvia layers surround a conventional core. A 1+N+1 build laminates one microvia layer onto each side of an N-layer core: one lamination cycle, one laser drilling pass per side. A 2+N+2 adds a second cycle, enabling microvias two layers deep and copper-filled stacked structures. Each added cycle repeats lamination, drilling, and plating—and multiplies both cost and cumulative yield risk.

The practical guidance: exhaust what 1+N+1 can do before specifying more. A 1+N+1 with well-planned staggered vias and both outer layers used for escape routing handles most 0.5 mm pitch BGAs. Reserve 2+N+2 for 0.4 mm pitch and genuinely dense designs, and treat 3+N+3 or any-layer construction as a deliberate, costed decision—these builds are standard in smartphones but rarely necessary in industrial products.

Fine-pitch BGA fields often leave no room for dog-bone fanouts, forcing vias directly into component pads. An open via in a pad wicks solder away during reflow and causes voids, so via-in-pad requires filling the via (usually with non-conductive epoxy resin), capping it with plated copper, and planarizing the surface flat. This is a mature process, but it adds measurable cost per board.

Flag every via-in-pad location in your fabrication notes. A fabricator who discovers unmarked via-in-pad during tooling either stops for clarification—costing you days—or quotes wrong. Also decide early whether microvias in pads can be left unfilled: shallow microvias with proper capture pads often reflow acceptably without fill, saving a process step, but this depends on paste volume and package type.

First, lamination cycle count—the dominant driver, as each cycle adds process time and compounds yield loss. Second, stacked versus staggered vias: stacked structures need copper filling and planarization at every level. Third, line width and spacing: dropping below 0.075 mm (3 mil) pushes imaging and etch capability and lowers yield. Fourth, via-in-pad fill and cap plating, priced per panel. Fifth, material selection: low-loss laminates for high-speed HDI can multiply raw material cost.

When cost matters, share your escape routing problem rather than a fixed stackup. During DFM review we frequently find that a design specified as 2+N+2 routes cleanly as 1+N+1 with staggered vias and adjusted fanout—a change that can cut bare-board cost by a third without touching the schematic.

Confirm aspect ratios on every microvia layer pair. Mark via-in-pad locations and fill requirements in fab notes. Include a stackup drawing with target thicknesses and impedance tables. State whether stacked vias are required or whether staggered equivalents are acceptable. Balance copper distribution across layers to control warp. And include the BGA land pattern datasheets for your finest-pitch parts—they anchor the entire escape routing review.

An HDI quote grounded in these details comes back faster and holds through production. If any of these items are still open questions in your design, send the RFQ anyway and say so: resolving them during engineering review costs nothing compared to a re-spin.